The present invention relates generally to an integrated circuit, a semi-conductor component, an electronic system, and a method for operating an integrated circuit.
Semi-conductor components, for example, corresponding integrated (analog and/or digital) circuits, semi-conductor memory components such as for instance function memory components (PLAs, PALs, etc.) and table memory components (for example, ROMs or RAMs, particularly SRAMs and DRAMs), etc. are subjected to numerous tests in the course of the manufacturing process.
For the simultaneous manufacture of a plurality of (generally identical) semi-conductor components or integrated circuits, a wafer (for example, a thin disk consisting of monocrystalline silicon) is used. The wafer is appropriately processed (for example, subjected to numerous of coating, lighting, etching, diffusion implantation processes, etc.), and subsequently sawn up (or for example, scored and snapped off), so that the individual components/integrated circuits/chips are made available.
During the manufacture of semi-conductor components/integrated circuits the components/circuits still on the wafer and incomplete may be subjected to corresponding test procedures (for example, kerf measurements) even before all the required above processing steps have been performed on the wafer (that is, even while the semi-conductor components/integrated circuits are still semi-complete). This may be done at one or several test stations by using one or several test apparatuses.
After the semi-conductor components/integrated circuits have been completed (that is, after all the above wafer processing steps have been executed) the semi-conductor components/integrated circuits are subjected to further test procedures at one or several (further) test stations—for instance the components still present on the wafer and completed may be tested with the help of corresponding (further) test apparatuses (“disk tests”).
In similar fashion several further tests may be performed (at corresponding further test stations and by using additional corresponding test apparatuses) for example, after the semi-conductor components/integrated circuits/chips have been installed in corresponding semi-conductor component housings, and/or for example, after the semi-conductor component housings (together with the semi-conductor components/integrated circuits/chips installed in them) have been installed in corresponding electronic modules (so-called “module tests”).
With the aid of above test procedures, for example, defective semi-conductor components/chips/modules can be identified and then eliminated (or else partially repaired), and/or the process parameters—used during the manufacture of the components in each case—can be appropriately modified and/or optimized in accordance with the test results achieved, and/or respective trimmings can be performed, etc.
For carrying out the above tests, the semi-conductor components/integrated circuits/chips may be brought from a normal operating mode to a test mode.
In the test mode, for instance, chip-internal data not accessible during the normal operating mode may be read.
In one embodiment, in the test mode, data may be written onto storage locations not accessible during the normal operating mode.
For instance, in the test mode, a serial number (ChipID) unique for a respective semi-conductor component/integrated circuit/chip may be read by the respective test apparatus. Further, in the test mode, data may be written into a chip-internal EEPROM used for trimming respective amplifier parameters of the semi-conductor component/integrated circuit/chip, etc.
For the test mode, one or several separate pins/pads may be provided at the respective semi-conductor component/integrated circuit/chip. These pins/pads are exclusively used during the test mode, and not during the normal operating mode. However, this approach leads to a relatively large total number of pins/pads.
In one embodiment, one or several pins/pads during the test mode might have a different function than during the normal operating mode. This approach, however, might lead to an enhanced complexity of the respective integrated circuit.
For these or other reasons, there is a need for the present invention.